A very important device of the type characterized generally above is the self-aligned gate MESFET. Self-aligned gate technology is adapted to enhance high frequency performance by using the gate as a mask to create the FET source and drain, thereby to obtain almost perfect alignment between those elements. In addition, as such circuits become miniaturized for purposes such as MMIC's (monolithic microwave integrated circuits), it is important to increase circuit density which requires precise alignment between multiple layers as they are deposited one upon the other during the semiconductor fabrication process.
The prior art has employed refractory metal gates as the mask or a portion of the mask for ion implantation steps. One prior art technique utilizing a refractory metal gate is described in connection with FIGS. 3(a)-3(h). Those figures show cross-sectional structures illustrating the process steps of one prior art method for producing a MESFET device.
FIG. 3(a) shows an early stage of device production in which an active layer 3 is formed in a semi-insulating GaAs substrate 1 by ion implantation An SiO.sub.2 film (not illustrated) is first formed on the substrate 1 as a surface protection film having a thickness of about 300 .ANG.. A resist pattern (not illustrated) is then formed onto the SiO.sub.2 film and Si ions are implanted selectively through the SiO.sub.2 film utilizing the resist pattern as a mask. The Si ions are implanted at about 50 keV to a concentration of 1.0 to 3.0.times.10.sup.12 cm.sup.-2. The resist pattern is removed and the implanted substrate 1 is annealed to form the active layer 3.
A refractory metal gate 2 is then formed by depositing an appropriate refractory metal alloy onto the active layer 3. The refractory metal layer 2 can be tungsten silicide (WSi), tungsten nitride (WN), tungsten silicon nitride (WSiN), or tungsten aluminum (WA1), for example, deposited onto the active layer 3 to a thickness of about 3000 .ANG.. The gate metal 2 is patterned by a photoresist layer 4 which is exposed and processed to protect the gate region, while leaving the remaining areas of the layer 2 exposed to an etching process.
Referring to FIG. 3(b), it is seen that the gate electrode 2 has been formed by etching away the exposed portion of the layer 2 not covered by the photoresist layer 4 and then removing the remaining photoresist layer 4. The gate electrode 2 then serves as a mask for formation of an initial low ion concentration portion 5 of the source and drain regions.
Advancing to FIG. 3(c), an insulating film or layer (not illustrated) is formed over the entire surface of the substrate 1. The insulating layer is anisotropically etched such as by reactive ion etching (RIE) to form side walls 7 adjacent the gate 2. The side walls 7 and the gate 2 then are utilized as a mask to form high ion concentration source and drain regions 6, again by ion implantation. The insulating side walls 7 then are removed.
As shown in FIG. 3(d), an insulating film or layer 20 then is deposited over the substrate 1 and the gate 2 by a conventional plasma CVD technique. Following the deposition of the layer 20, a photoresist layer 9 is formed over the layer 20 to form a flat top surface, as illustrated in FIG. 3(e). The layer 9 and the layer 20 are formed such that they will etch at substantially the same rate.
The layers 9 and 20 are etched together under tightly controlled conditions until the top of the gate 2 is exposed as shown in FIG. 3(f). Next a resist layer 10 is patterned to leave an opening adjacent the gate 2 as illustrated in FIG. 3(g). Subsequently, a low resistance metal layer 11 is deposited on the gate 2 and the resist layer 10 (not illustrated). The metal layer 11 such as Ti/Mo/Au, is removed with the layer 10, such as by a conventional lift-off technique, leaving the low resistance contact 11, as shown in FIG. 3(h). It is seen that the low resistance gate contact 11 covers the gate 2 and overlaps the gate to cover portions of the insulating film 20 over the source and drain regions near the gate, including the low concentration source and drain regions 5.
In forming the prior art semiconductor devices, the resist 9 and the insulating film 20 must be etched at substantially equal rates and the etching process must be stopped at the stage shown in FIG. 3(f). The etching has to consistently be stopped such that the top of the gate 2 is just exposed. If the etching is continued, or is uneven, the gate metal 2 also will be etched away. This results in semiconductor devices which are not uniform and are not easily reproducible, which provides poor reliability of the semiconductor devices.